Technical Field
The present invention relates to a semiconductor device, and, for example, a technique applicable to a semiconductor device having transistors and interconnects.
Related Art
When semiconductor chips are used, the semiconductor chips are required to be connected to an external terminal such as a lead terminal by a bonding wire or the like.
A technique relating to a semiconductor device using a bonding wire includes, for example, a technique disclosed in Japanese Unexamined Patent Publication No. 2000-133730. In Japanese Unexamined Patent Publication No. 2000-133730, a bipolar transistor and a unipolar transistor are formed in a semiconductor chip. The same wire is connected to an interconnect which is connected to the emitter electrode of the bipolar transistor at a plurality of points. In addition, the same wire is connected to an interconnect which is connected to a drain electrode of the unipolar transistor at a plurality of points. Japanese Unexamined Patent Publication No. 2000-133730 discloses that the delay time of a response of a transistor is shortened with an increase in the number of connecting points of the wire.
On the other hand, transistors using a compound semiconductor layer as a channel have been recently developed. Such transistors have a feature of low on-resistance.
Meanwhile, Japanese Unexamined Patent Publication No. 2009-206140 and Japanese Unexamined Patent Publication No. 2011-210771 disclose that in a semiconductor device having an insulated gate bipolar transistor (IGBT), the wire is connected to the surface electrode of the IGBT at a plurality of points.
In semiconductor devices having a transistor, lowering an on-resistance is required. Such an on-resistance includes a component caused by a transistor and a component caused by an interconnect. The inventors have studied lowering the resistance component caused by an interconnect. Other problems and novel features will be made clearer from the description and the accompanying drawings of the present specification.